For integrated circuits, power consumption is not only an issue in a functional mode but also in a test mode. Scan-based testing is a widely adopted test strategy for integrated circuits. An integrated circuit's power dissipation during scan testing can be significantly higher than that during normal operation. In a full-scan circuit, it is possible that the test power consumption exceeds the circuit's power rating in both a shift mode and a capture mode.
The difference in power consumption between a test mode and a normal functional mode is because test patterns in the test mode can switch as many nodes as possible while the normal functional mode typically activates a much fewer number of modules at a given time.
Another reason in the difference in power consumption between the test mode and the normal functional made is that successive functional input vectors applied to an integrated circuit during the normal functional mode have a significant correlation, while the correlation between consecutive test patterns can be very low.
Power consumption during the test mode thus has two main components: average power and peak power. Average power is the total distribution of power over a time period, which is generally the amount of power consumed during the application of a test. An elevated average power adds to the thermal load that is to be vented away from the circuit under test. An increased thermal load may cause structural damage to the silicon (hot spots), to bonding wires or to the package. Other thermal effects such as hot-carrier-induced defects, electro migration and dielectric breakdown are accelerated gradually and may affect performance or cause failures over time. This is especially a serious problem for low-power circuits, which usually have low heat dissipation limits. All of the above cause circuit reliability concerns.
Peak power is the highest permissible value of power at any given instant. The peak power determines the thermal and electrical limits of components and the system packaging requirements. If wafer probes have higher inductance than supply pins, a resulting excessive power/ground noise can erroneously change behavior of the circuit. As a result, correct functioning of the entire circuit is no longer insured. Further, an unanticipated voltage drop may also cause the circuits to run at a lower speed, thus leading to performance failures. For example, a worst case voltage drop of 10% can increase the circuit delay by up to 15%.
Generally, peak power consumption during a shift mode occurs with the simultaneous toggling of shift clocks. In the shift mode, the complete clock network feeding the scan flip-flops toggles as all the clock gating cells are in a transparent mode. The flip-flop switching activity also adds to the power consumption.
In a full-scan design, where all clocks are applied simultaneously, this typically occurs at the point during the load/unload process where the largest number of differences between adjacent scan cells exist. This typically occurs during the first unload cycle, right after capture cycles. Average power consumption during the shift mode is equal to the sum of the power consumptions over all the shift cycles, divided by the total number of shift cycles. Both peak and average power consumption should be managed during the shift mode, since peak power consumption can cause power line drop, while average power consumption can cause overheating to occur over time.
During the capture mode, the power consumption may exceed the limit as the switching activity can be much higher as compared to a normal functional mode. A higher peak power during the capture mode can contribute enough of a current-resistance (IR) drop to cause false logic values to transition within the capture time window causing the test pattern to fail. Although this issue is associated with both stuck-at and transition delay tests, it is more common in delay-dependent at-speed transition test patterns.
In current low power designs, there are different strategies to reduce power consumption during the functional mode. Clock gating, multi-supply voltage and power shut-off techniques are widely used for power management. For the test mode, the power can be reduced both by hardware and software techniques.
A number of approaches have been used for reducing power consumption during test. These approaches include over-sizing power supply and package cooling to withstand the increased current during testing, or reducing the test operation frequency. Unfortunately, these approaches increase either hardware cost or test time and may lead to a loss of test coverage as at-speed defects may be masked.
Other approaches for reducing power consumption during test include reducing the switching activities to levels comparable with the functional modes. Test scheduling algorithms, for example, may be used to determine the functional logic blocks of a complex design to be activated in parallel at each stage of the test session to reduce the number of concurrently tested modules. The average test power is reduced but the total test time is increased. Low power automatic test pattern generation (ATPG) algorithms generate test patterns to reduce test power in addition to the traditional ATPG objectives of fault coverage and test length. Clock gating for capture power reduction has also been used. A clock disabling technique utilizes clock gating cells to keep some scan flip-flops in stable states.
Another approach is based on dynamic scan chain partitioning, as disclosed in U.S. Pat. No. 7,937,634. Peak power is reduced by dynamically partitioning scan chains into multiple groups, wherein transitions are equally distributed among these multiple groups. For each test pattern, a particular partitioning that leads to the even partitioning of the transitions is computed by analyzing the transition distribution of the pattern. The scan chain partitioning is formulated using an Integer Linear Programming (ILP) and an efficient greedy heuristic. The computed information is loaded into the reconfigurable scan chain partitioning hardware during the capture window. The partitioning hardware is composed of controllable clock gating logic, which is reconfigured on a per pattern basis, wherein the reconfiguration is effected by only utilizing the existing scan channels.
Another approach is based on based on a selected clock order in a selected capture operation, as disclosed in U.S. Pat. No. 7,210,082. In this approach, the RTL (register-transfer level) or Gate-Level HDL (hardware description language) code is compiled based on the Input Constraints and a Foundry Library into a Sequential Circuit Model. The Sequential Circuit Model is then transformed into an equivalent Combinational Circuit Model for performing Forward and/or Backward Clock Analysis to determine the driving and observing clocks for all inputs and outputs of all combinational logic gates in the Combinational Circuit Model. The analysis results are used for Uncontrollable/Unobservable Labeling of selected inputs and outputs of the combinational logic gates. Finally, ATPG and/or Fault Simulation are performed according to the Uncontrollable/Unobservable Labeling to generate the HDL Test Benches and ATE Test Programs.
Scan chain and pattern re-ordering techniques to reduce the shift mode power have also been used to reduce power consumption during the test mode. These techniques modify either the order in which test patterns of a given test sequence are applied to the chip or the order in which the scan flip-flops are chained to form the scan chain. These techniques inherently require extra computations, thereby adding to the overall complexity. Experimental results show that scan cell ordering can reduce test power consumption by 10-25%. However, since there is an increase in routing congestion, the applicability of this technique is limited.
To reduce power in the shift mode, various X-fill techniques have been used. These techniques reduce flip-flop switching activity but the peak power issue may still occur since the complete clock network is toggling simultaneously. Clock scheme modification techniques include modifying the clock scheme connected to the circuit under test and to the scan chains to either partially disable the clock signal or to reduce the clock rate during the test session without increasing the test time. Multi-duty scan architecture reduces the peak power issue by spreading the clock edges between different scan chains but it suffers from implementation complexity, and a delay may be introduced which may change over time based on processing operations and external factors.